TRUTHFRAMER
TF-000003 · FPGA vs CPU Latency Boundary · Where did decision latency accumulate?
Truth score98.9
Clock skew12 ns
Replay divergence0.01 bps
Sequence gaps0
01 · Pipeline Delta
| Stage | FPGA ns | CPU ns | Δ |
|---|---|---|---|
| Packet decode | 82 | 420 | 338 |
| Feature extraction | 110 | 970 | 860 |
| Decision boundary | 64 | 1320 | 1256 |
| Risk check | 75 | 610 | 535 |
| Order encode | 58 | 330 | 272 |
02 · Latency Waterfall
03 · Stage Bars
Packet decode
82ns
Feature extraction
970ns
Decision boundary
1320ns
Risk check
610ns
Order encode
58ns
04 · Boundary Finding
Largest accumulation occurs at decision-boundary evaluation.
CPU path shows jitter expansion after feature extraction.
FPGA path compresses decode-to-encode interval.
Gateway handoff remains a shared terminal bottleneck.
05 · Frame Boundary
No investment advice
No trade recommendation
No broker execution
Does not claim production infrastructure performance
06 · Frame Identity
| Object | TRUTH_FRAME |
| Frame | tf_000003 |
| Replay | deterministic |
| Question | Where did decision latency accumulate? |